
-------------Din Generator---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Dinclk is
	port(	clk: in std_logic;
			SWT			: in std_logic;
			iyin 		: in std_logic_vector(7 downto 0);
			idin		: in std_logic_vector (11 downto 0);
			id			: out std_logic;
			idr			: out std_logic;
			clkout		: out std_logic
			);
END Dinclk;

ARCHITECTURE beh of Dinclk is

	TYPE STATETYPE IS (S0, S1, S2, S3, S4, S5, S6);
	SIGNAL currstate, nextstate: statetype;
	constant Dcon : std_logic_vector(11 downto 0) := "100111111110";
	constant Dcon2 : std_logic_vector(11 downto 0) := "000000000011";
	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
begin
state: PROCESS (currstate, SWT, iyin, idin)
		BEGIN
			CASE currstate IS
				WHEN S0 =>
					If (SWT = '1') then

						clkout <= '0';
						
						id <= '0';
						idr <= '1';
						
						nextstate <= S5;
					Else
						clkout <= '0';
						
						id <= '0';
						idr <= '1';
						
						nextstate <= S0;
					End if;
					
				WHEN S1 =>
					
					clkout <= '0';
					
					id <= '1';
					idr <= '0';
					if (idin = Dcon2) then
						nextstate <= S3;
					else
						nextstate <= S2;
					End if;
					
					
				WHEN S2 =>
					
					clkout <= '0';
					
					id <= '1';
					idr <= '0';
					
					if (idin = Dcon2) then
						nextstate <= S3;
					else
						nextstate <= S1;
					End if;
				
				WHEN S3 =>
					
					clkout <= '1';
					
					id <= '1';
					idr <= '0';
					
					if (idin = Dcon + Dcon2) then
						nextstate <= S5;
					else
						nextstate <= S4;
					End if;
					
					
				WHEN S4 =>
					
					clkout <= '1';
					
					id <= '1';
					idr <= '0';
					
					if (idin = Dcon + Dcon2) then
						nextstate <= S5;
					else
						nextstate <= S4;
					End if; 
					
				WHEN S5 =>
						
					clkout <= '0';
					
					id <= '0';
					idr <= '1';
					
					If (iyin = Ycon)then
						nextstate <= S1;
					else
						nextstate <= S6;
					End if;
					
				WHEN S6 =>
						
					clkout <= '0';
					
					id <= '0';
					idr <= '1';
					
					If (iyin = Ycon)then
						nextstate <= S1;
					else
						nextstate <= S5;
					End if;
					
				END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				IF (SWT = '0') THEN
					currstate <= S0;
				ELSE
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
		
end beh;

----------XYclk-------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity XYclk is
	 port(	clk			: in std_logic;
			SWT			: in std_logic;
			ixin		: in std_logic_vector(7 downto 0);
			ix			: out std_logic;
			ixr			: out std_logic;
			iyin		: in std_logic_vector(7 downto 0);
			iy			: out std_logic;
			iyr			: out std_logic;
			clkout		: out std_logic_vector (1 downto 0)
			);
end XYclk;

architecture Behavioral of XYclk is

	TYPE STATETYPE IS (S0, S1, S2, S3, S4, S3c, S3b);
	SIGNAL currstate, nextstate: statetype;

	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
	constant Xcon : std_logic_vector(7 downto 0) := "10011111";

	
begin
state: PROCESS (currstate, SWT, ixin, iyin)
		BEGIN
			CASE currstate IS
				WHEN S0 =>
					IF (SWT = '1') THEN
						clkout(1) <= '1';
						clkout(0) <= '1';
						
						iy <= '0';
						iyr <= '1';
						ix <= '0';
						ixr <= '1';

				
						nextstate <= S1;	
					ELSE
						clkout(1) <= '0';
						clkout(0) <= '0';
						
						iy <= '0';
						iyr <= '1';
						ix <= '0';
						ixr <= '1';
	
						
						nextstate <= S0;
					END IF;
					
				WHEN S1 =>
					clkout(1) <= '0';
					clkout(0) <= '0';
				
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					if (ixin = Xcon) then
						if (iyin = Ycon) then
							nextstate <= S4;
						else
							nextstate <= S3;
						end if;	
					
					else
						nextstate <= S2;
					end if;

				WHEN S2 =>	
					
					clkout(1) <= '0';
					clkout(0) <= '1';	
									
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';

					nextstate <= S1;
									
				WHEN S3 =>
					
					clkout(1) <= '1';
					clkout(0) <= '1';	
					
					iy <= '1';
					iyr <= '0';
					ix <= '0';
					ixr <= '1';

					nextstate <= S3b;
					
				WHEN S3b =>
					
					clkout(1) <= '1';
					clkout(0) <= '0';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '0';
					ixr <= '0';

					nextstate <= S3c;
				
				WHEN S3c =>
					
					clkout(1) <= '0';
					clkout(0) <= '1';	
					
					iy <= '0';
					iyr <= '0';
					ix <= '1';
					ixr <= '0';

					nextstate <= S1;
					
				WHEN S4 =>
				
					clkout(1) <= '1';
					clkout(0) <= '1';	
					
					iy <= '0';
					iyr <= '1';
					ix <= '0';
					ixr <= '1';

					nextstate <= S1;					
				
			END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				IF (SWT = '0') THEN
					currstate <= S0;
				ELSE
					currstate <= nextstate;
				END IF;
			END IF;
		END PROCESS statereg;
					
			
end Behavioral;

-----------3bit d flipflop------------------

library ieee ;
use ieee.std_logic_1164.all;
use work.all;

entity My_dff is
	port(	clk			: in std_logic;
			data_in		: in std_logic_vector (2 downto 0);
			data_out	: out std_logic_vector (2 downto 0)
		);
end My_dff;

architecture behv of My_dff is
begin

    process(data_in, clk)
    begin

        -- clock rising edge

	if (clk='1' and clk'event) then
	    data_out <= data_in;
	end if;

    end process;	

end behv;

------2 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_2clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			SWT  		: in std_logic
			);
end My_2clkdiv;

architecture behavior of My_2clkdiv is
	constant num : integer := 2;
	signal cnt : integer := 0;
	begin
		process(clk, SWT)
			begin
				if(clk'event and clk='1' and SWT = '1') then
					if(cnt > (num/2 - 1))then
						clkout <= '0';
						cnt <= cnt+1;
						if(cnt = num-1)then
							cnt <= 0;
						end if;
					else
						cnt <= cnt+1;
						clkout <='1';
					end if;
				END if;
		end process;
end behavior;

------8 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_8clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			SWT  		: in std_logic
			);
end My_8clkdiv;

architecture behavior of My_8clkdiv is
	constant num : integer := 8;
	signal cnt : integer := 0;
	begin
		process(clk, SWT)
			begin
				if(clk'event and clk='1' and SWT = '1') then
					if(cnt > (num/2 - 1))then
						clkout <= '0';
						cnt <= cnt+1;
						if(cnt = num-1)then
							cnt <= 0;
						end if;
					else
						cnt <= cnt+1;
						clkout <='1';
					end if;
				END if;
		end process;
end behavior;

------ 16 Cycle Clock Divider-------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

entity My_16clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			SWT  		: in std_logic
			);
end My_16clkdiv;

architecture behavior of My_16clkdiv is
	constant num : integer := 16;
	signal cnt : integer := 0;
	begin
		process(clk, SWT)
			begin
				if(clk'event and clk='1' and SWT = '1') then
					if(cnt > (num/2 - 10))then
						clkout <= '0';
						cnt <= cnt+1;
						if(cnt = num-10)then
							cnt <= -9;
						end if;
					else
						cnt <= cnt+1;
						clkout <='1';
					end if;
				END if;
		end process;
end behavior;

----------8bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_8bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (7 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_8bCounter;  

ARCHITECTURE behav OF My_8bCounter IS
	SIGNAL buff : std_logic_vector (7 downto 0) := "00000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "00000000";
			else
				if (count = '1') then
					buff <= buff + "00000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------12bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_12bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (11 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_12bCounter;  

ARCHITECTURE behav OF My_12bCounter IS
	SIGNAL buff : std_logic_vector (11 downto 0) := "000000000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000000000000";
			else
				if (count = '1') then
					buff <= buff + "000000000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

---------- 18bit Counter ----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY My_18bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END My_18bCounter;  

ARCHITECTURE behav OF My_18bCounter IS
	SIGNAL buff : std_logic_vector (17 downto 0) := "000000000000000000";
BEGIN
	PROCESS(reset, count, clk) 
	BEGIN
		IF (clk = '1' and clk'event) THEN
			if (reset = '1') then
				buff <= "000000000000000000";
			else
				if (count = '1') then
					buff <= buff + "000000000000000001";
				end if;
			end if;	
		END if;	
   END PROCESS;
	counter <= buff;
END behav;

----------Print Screen----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity My_printsceern is
	port(
			clk		: in std_logic;
			SWT   	: in STD_logic;
			data_inU: in STD_logic_vector (15 downto 0);
			data_inL: in STD_logic_vector (15 downto 0);
			GPIO_1	: inout STD_logic_vector (7 downto 0)
		);
end My_printsceern;

architecture beh of My_printsceern is

	TYPE STATETYPE IS (S0, S1, S2, S3);
	SIGNAL currstate, nextstate: statetype;
	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
	
begin
state: PROCESS (currstate, SWT, data_inU, data_inL)
		BEGIN
			CASE currstate IS
				WHEN S0 =>
					GPIO_1 (3 downto 0) <= data_inU (3 downto 0);
					GPIO_1 (7 downto 4) <= data_inL (3 downto 0);
					nextstate <= S1;
					
				WHEN S1 =>
				
					GPIO_1 (3 downto 0) <= data_inU (7 downto 4);
					GPIO_1 (7 downto 4) <= data_inL (7 downto 4);
					nextstate <= S2;
					
				WHEN S2 =>
				
					GPIO_1 (3 downto 0) <= data_inU (11 downto 8);
					GPIO_1 (7 downto 4) <= data_inL (11 downto 8);
					nextstate <= S3;
					
				WHEN S3 =>
				
					GPIO_1 (3 downto 0) <= data_inU (15 downto 12);
					GPIO_1 (7 downto 4) <= data_inL (15 downto 12);
					nextstate <= S0;
					
				END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				
					currstate <= nextstate;
			
			END IF;
		END PROCESS statereg;
					
			
end beh;

------------sram control----------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity My_sramctrl is
	port(
			clk			: in std_logic;
			SWT   		: in STD_logic;
			iyin		: in STD_logic_vector (7 downto 0);
			
			SRAM_ADDR 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N 	: OUT STD_LOGIC;
			SRAM_OE_N 	: OUT STD_LOGIC;
			SRAM_CE_N 	: OUT STD_LOGIC;
			SRAM_UB_N 	: OUT STD_LOGIC;
			SRAM_LB_N 	: OUT STD_LOGIC;
			SRAM_DQ 	: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			
			adcounter	: in std_logic_vector (17 downto 0);
			adcount 	: out std_logic;
			adreset		: out std_logic;
			
			Ur_reset 	: OUT std_logic;
			Ur_load 	: OUT std_logic;
			Ur_data_in	: OUT std_logic_vector (15 downto 0);
			Lr_reset 	: OUT std_logic;
			Lr_load 	: OUT std_logic;
			Lr_data_in	: OUT std_logic_vector (15 downto 0)
			);
end My_sramctrl;

architecture beh of My_sramctrl is

	TYPE STATETYPE IS (S0U, S0L, S1U, S1L);
	SIGNAL currstate, nextstate: statetype;
	constant Ycon : std_logic_vector(7 downto 0) := "11101111";
	constant ad_zero : std_logic_vector(17 downto 0) := "000000000000000000";
	constant ad_middle : std_logic_vector(17 downto 0) := "000000010011100111";
begin
state: PROCESS (currstate, SWT, iyin, SRAM_DQ, adcounter)
		BEGIN
			CASE currstate IS
				WHEN S0U =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= ad_zero;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '0';
					adreset <= '1';
					
					Ur_reset <= '0';
					Ur_load <= '1';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					nextstate <= S0L;
				WHEN S0L =>
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= ad_middle;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '0';
					adreset <= '1';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '1';
					
					nextstate <= S1U;
					
				WHEN S1U =>
				
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= adcounter;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '1';
					adreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '1';
					Lr_reset <= '0';
					Lr_load <= '0';
					
					nextstate <= S1L;
				WHEN S1L =>
				
					Ur_data_in <= SRAM_DQ;
					Lr_data_in <= SRAM_DQ;
					
					SRAM_ADDR <= adcounter + ad_middle;
					
					SRAM_WE_N <= '1';
					SRAM_OE_N <= '0';
					SRAM_CE_N <= '0';
					SRAM_UB_N <= '0';
					SRAM_LB_N <= '0';
					
					adcount <= '0';
					adreset <= '0';
					
					Ur_reset <= '0';
					Ur_load <= '0';
					Lr_reset <= '0';
					Lr_load <= '1';
					
					if (iyin = Ycon) then
						nextstate <= S0U;
					else
						nextstate <= S1U;
					end if;
					
				END CASE;
		END PROCESS state;
		
		
		Statereg: PROCESS (clk)
		BEGIN
			IF (clk = '1' and clk'event) THEN
				
					currstate <= nextstate;
			
			END IF;
		END PROCESS statereg;
					
			
end beh;

---------- 16 Bit Register ----------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

---------------------------------------------------

entity My_16bRegister is

generic(n: natural :=2);
	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector ( 15 downto 0);
			data_out	: OUT std_logic_vector (15 downto 0)
			);
end My_16bRegister;

----------------------------------------------------

architecture behv of My_16bRegister is

    signal Q_tmp: std_logic_vector(15 downto 0);

begin

    process(clk, reset, data_in, load)
    begin

	if reset = '0' then
            -- use 'range in signal assigment 
            Q_tmp <= (Q_tmp'range => '0');
	elsif (clk='1') then
	    if load = '1' then
		Q_tmp <= data_in;
	    end if;
	end if;

    end process;

    -- concurrent statement
    data_out <= Q_tmp;

end behv;

---------Top level--------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity toplevel is
	port(	CLOCK_50	: in std_logic;
			SW			: in STD_logic_vector (17 downto 0);
			SRAM_ADDR	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N	: OUT STD_LOGIC;
			SRAM_OE_N	: OUT STD_LOGIC;
			SRAM_CE_N	: OUT STD_LOGIC;
			SRAM_UB_N	: OUT STD_LOGIC;
			SRAM_LB_N	: OUT STD_LOGIC;
			SRAM_DQ		: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			GPIO_1		: inout STD_logic_vector (35 downto 0)
			);
end toplevel;

Architecture struct of toplevel is

component Dinclk is
	port(	clk			: in std_logic;
			SWT			: in std_logic;
			iyin 		: in std_logic_vector(7 downto 0);
			idin		: in std_logic_vector (11 downto 0);
			id			: out std_logic;
			idr			: out std_logic;
			clkout		: out std_logic
			);
END component;

component XYclk is
	port(	clk			: in std_logic;
			SWT			: in std_logic;
			ixin		: in std_logic_vector(7 downto 0);
			ix			: out std_logic;
			ixr			: out std_logic;
			iyin		: in std_logic_vector(7 downto 0);
			iy			: out std_logic;
			iyr			: out std_logic;
			clkout		: out std_logic_vector (1 downto 0)
			);
end component;

component My_dff is
	port(	clk			: in std_logic;
			data_in		: in std_logic_vector (2 downto 0);
			data_out	: out std_logic_vector (2 downto 0)
		);
end component;

component My_2clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			SWT  		: in std_logic
			);
end component;

component My_8clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			SWT  		: in std_logic
			);
end component;

component My_16clkdiv is
	port(	clk 		: in std_logic;
			clkout 		: out std_logic;
			SWT  		: in std_logic
			);
end component;

component My_8bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (7 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component;

component My_12bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (11 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
END component;

component My_18bCounter IS
	PORT(	clk 		: in std_logic;
			counter		: OUT std_logic_vector (17 downto 0);
			count 		: IN std_logic;
			reset		: IN std_logic
			);
end component;  

component My_printsceern is
	port(
			clk			: in std_logic;
			SWT			: in STD_logic;
			data_inU	: in STD_logic_vector (15 downto 0);
			data_inL	: in STD_logic_vector (15 downto 0);
			GPIO_1		: inout STD_logic_vector (7 downto 0)
			);
end component;

component My_sramctrl is
	port(
			clk			: in std_logic;
			SWT   		: in STD_logic;
			iyin		: in STD_logic_vector (7 downto 0);
			
			SRAM_ADDR 	: OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
			SRAM_WE_N 	: OUT STD_LOGIC;
			SRAM_OE_N 	: OUT STD_LOGIC;
			SRAM_CE_N 	: OUT STD_LOGIC;
			SRAM_UB_N 	: OUT STD_LOGIC;
			SRAM_LB_N 	: OUT STD_LOGIC;
			SRAM_DQ 	: INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
			
			adcounter	: in std_logic_vector (17 downto 0);
			adcount 	: out std_logic;
			adreset		: out std_logic;
			
			Ur_reset 	: OUT std_logic;
			Ur_load 	: OUT std_logic;
			Ur_data_in	: OUT std_logic_vector (15 downto 0);
			Lr_reset 	: OUT std_logic;
			Lr_load 	: OUT std_logic;
			Lr_data_in	: OUT std_logic_vector (15 downto 0)
			);
end component;

component My_16bRegister IS
	PORT(	clk 		: IN std_logic;
			reset 		: IN std_logic;
			load 		: IN std_logic;
			data_in 	: IN std_logic_vector ( 15 downto 0);
			data_out	: OUT std_logic_vector (15 downto 0)
			);
END component;  

SIGNAL clk2, clk8, clk16, resetx, countx, resety, county, resetdin, countdin, adcount, adreset, Din_clk, UR_reset, UR_load, LR_reset, LR_load: std_logic;
SIGNAL XY_clk 					: std_logic_vector (1 downto 0);
SIGNAL XYD_in, XYD_out 			: std_logic_vector (2 downto 0);
SIGNAL xval, yval, dataout		: std_logic_vector(7 downto 0);
SIGNAL dinval					: std_logic_vector(11 downto 0);
SIGNAL UR_data_in, UR_data_out, LR_data_in, LR_data_out: std_logic_vector(15 downto 0);
SIGNAL adcounter				: std_logic_vector(17 downto 0);

begin
	clkdiv_2	: My_2clkdiv		port map (CLOCK_50, clk2, SW(1));
	clkdiv_8	: My_8clkdiv		port map (CLOCK_50, clk8, SW(1));
	clkdiv_16	: My_16clkdiv		port map (CLOCK_50, clk16, SW(1));
	XY_1		: XYclk				port map (clk8, SW(0), xval, countx, resetx, yval, county, resety, XY_clk);
	Din			: Dinclk			port map (CLOCK_50, SW(0), yval, dinval, countdin, resetdin, Din_clk);
	xcount		: My_8bCounter		port map (clk8, xval, countx, resetx);
	ycount		: My_8bCounter		port map (clk8, yval, county, resety);
	dincount	: My_12bCounter		port map (CLOCK_50, dinval, countdin, resetdin);
	add_counter	: My_18bCounter		port map (clk16, adcounter, adcount, adreset);
	gfilter		: My_dff			port map (CLOCK_50, XYD_in, XYD_out);
	upper_reg	: My_16bregister	port map (clk16, UR_reset, UR_load, UR_data_in, UR_data_out);
	lower_reg	: My_16bregister	port map (clk16, LR_reset, LR_load, LR_data_in, LR_data_out);
	pscreen		: My_printsceern	port map (clk16, SW(0), UR_data_out, LR_data_out, dataout);
	sramcontrol	: My_sramctrl		port map (CLOCK_50, SW(0), yval, SRAM_ADDR, SRAM_WE_N, SRAM_OE_N, SRAM_CE_N, SRAM_UB_N, SRAM_LB_N, SRAM_DQ, adcounter, adcount, adreset, UR_reset, UR_load, UR_data_in, LR_reset, LR_load, LR_data_in);
	
	XYD_in(1 downto 0) <= XY_clk;
	XYD_in(2) <= Din_clk;
	
	GPIO_1 (13)	<= '0';
	GPIO_1 (15)	<= XYD_out(0);
	GPIO_1 (19)	<= XYD_out(1);
	GPIO_1 (17)	<= XYD_out(2);
	GPIO_1 (21) <= dataout(0);
	GPIO_1 (23) <= dataout(1);
	GPIO_1 (25) <= dataout(2);
	GPIO_1 (27) <= dataout(3);
	GPIO_1 (29) <= dataout(4);
	GPIO_1 (31) <= dataout(5);
	GPIO_1 (33) <= dataout(6);
	GPIO_1 (35) <= dataout(7);
	
End struct;
